A single modern processors can have four, eight, or more cores, but the way they communicate is far from efficient. Currently, groups of wires called buses connect the cores, letting two of them at a time communicate. That works fine for smaller chips, but as engineers scale up the number of cores, they'll need a new solution. This June, Associate Professor Li-Shiuan Peh of MIT and her colleagues will present a paper summarizing ten years of research on a "network on chip" solution, which would allow data to be transmitted in packets similar to those used online.

Peh's proposed network would solve both the scaling problem of buses (which only work for up to about eight cores) and would reduce the power consumption associated with them. In her solution, short wires would connect each core to the four cores around it, rather than routing long wires around all the cores. Packets of data would then be transferred through the cores, with a set of routers signaling whether a packet should be inspected or passed through to its destination.

Creating such a network would be challenging, particularly because "people don’t know how to build these networks, because it has been buses for decades." There are also speed and design limitations that would have to be overcome, like the aforementioned fact that routers would need to switch packets through multiple cores. Peh and others will present their research at the Design Automation Conference in New Orleans.