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Intel demos first Lakefield chip design using its 3D stacking architecture

Intel demos first Lakefield chip design using its 3D stacking architecture


The Foveros era at Intel is approaching

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Intel is making progress on developing its next-generation 10-nanometer processors, and today during its CES press conference, the chipmaker showed off the first completed designs for what the company is calling Lakefield. Based on the Foveros 3D design that was first outlined last month, Lakefield is effectively a stacked processor, similar to how chipmakers can now stack memory, that lets Intel break out different PC components into separate “chiplets” that rest on top of one another to create a full system-on-a-chip.

The benefits of stacking are that you can make something small — in this case, an entire computer board that’s no bigger than five quarters laid end to end.

Because of its tiny form factor, the board opens up new possibilities for lighter laptops and longer-lasting portable devices with unique form factors, including foldable phones and tablets that would require the chip to take up much less real estate. Intel had a few working prototypes here at CES, on stage. Intel says Lakefield combines a new Sunny Cove core, which is based on the same microarchitecture that will power Intel’s next-generation Core chips, with four low-power Atom cores, so it should pack surprising performance into a small package.

Image: Intel

Lakefield is also a promising step in helping Intel avoid continued 10nm failures, since the delay of its Cannon Lake chip architecture. In its CES press conference, Intel also announced the new Ice Lake architecture, which is slated to ship in devices starting later this year, as well as 10nm silicon for the datacenter. Ice Lake is for much more powerful machines, while Lakefield will specialize in lower-power devices with unique hardware constraints, including foldable phones and tablets, drones, smart home devices, and other gadgets that require a tiny, all-in-one chip.